SIMD - BHC Documentation

data Vec2F32 { } #

Vec2F32

data Vec4F32 { } #

Vec4F32

data Vec8F32 { } #

Vec8F32

data Vec16F32 { } #

Vec16F32 !Vec8F32 !Vec8F32

data Vec2F64 { } #

Vec2F64

2-element double vector (128-bit).

data Vec4F64 { } #

Vec4F64

data Vec8F64 { } #

Vec8F64 !Vec4F64 !Vec4F64

data Vec2I32 { } #

Vec2I32

2-element int32 vector.

data Vec4I32 { } #

Vec4I32

data Vec8I32 { } #

Vec8I32 !Vec4I32 !Vec4I32

data Vec16I32 { } #

Vec16I32 !Vec8I32 !Vec8I32

16-element int32 vector (512-bit AVX-512).

data Vec2I64 { } #

Vec2I64

2-element int64 vector.

data Vec4I64 { } #

Vec4I64

data Vec8I64 { } #

Vec8I64 !Vec4I64 !Vec4I64

newtype Mask n { } #

Mask { maskBits :: Word64 }

SIMD mask for conditional operations.

class SIMDVec v { } #

Methods

vBroadcast :: (Elem v) -> v

vExtract :: v -> Int -> Elem v

vInsert :: v -> Int -> (Elem v) -> v

vWidth :: v -> Int

vAddImpl :: v -> v -> v

vSubImpl :: v -> v -> v

vMulImpl :: v -> v -> v

vDivImpl :: v -> v -> v

vSumImpl :: v -> Elem v

vProductImpl :: v -> Elem v

SIMD vector type class.

maskAll :: Mask n { } #

Mask with all bits set.

maskNone :: Mask n { } #

Mask with no bits set.

maskFromBits :: Word64 -> Mask n { } #

Create mask from bit pattern.

maskToBits :: (Mask n) -> Word64 { } #

Extract bit pattern from mask.

broadcast :: (SIMDVec v) => (Elem v) -> v { } #

Broadcast a scalar to all elements.

fromList :: (SIMDVec v) => [Elem v] -> v { } #

Create vector from list (must have correct length).

pack2 :: Float -> Float -> Vec2F32 { } #

Pack 2 scalars into a vector.

pack4 :: Float -> Float -> Float -> Float -> Vec4F32 { } #

Pack 4 scalars into a vector.

pack8 :: Float -> Float -> Float -> Float -> Float -> Float -> Float -> Float -> Vec8F32 { } #

Pack 8 scalars into a vector.

extract :: (SIMDVec v) => v -> Int -> Elem v { } #

Extract element at index.

toList :: (SIMDVec v) => v -> [Elem v] { } #

Convert vector to list.

unpack2 :: Vec2F32 -> (Float, Float) { } #

Unpack 2-element vector.

unpack4 :: Vec4F32 -> (Float, Float, Float, Float) { } #

Unpack 4-element vector.

unpack8 :: Vec8F32 -> (Float, Float, Float, Float, Float, Float, Float, Float) { } #

Unpack 8-element vector.

vAdd :: (SIMDVec v) => v -> v -> v { } #

Vector addition.

vSub :: (SIMDVec v) => v -> v -> v { } #

Vector subtraction.

vMul :: (SIMDVec v) => v -> v -> v { } #

Vector multiplication.

vDiv :: (SIMDVec v) => v -> v -> v { } #

Vector division.

vNeg :: (SIMDVec v) => v -> v { } #

Negate all elements.

vAbs :: (SIMDVec v, Num (Elem v), Ord (Elem v)) => v -> v { } #

Absolute value of all elements.

vSqrt :: (SIMDVec v, Floating (Elem v)) => v -> v { } #

Square root of all elements.

vRsqrt :: (SIMDVec v, Floating (Elem v)) => v -> v { } #

Reciprocal square root (fast approximation).

vRcp :: (SIMDVec v, Fractional (Elem v)) => v -> v { } #

Reciprocal (fast approximation).

vMin :: (SIMDVec v, Ord (Elem v)) => v -> v -> v { } #

Element-wise minimum.

vMax :: (SIMDVec v, Ord (Elem v)) => v -> v -> v { } #

Element-wise maximum.

vFMA :: (SIMDVec v, Num (Elem v)) => v -> v -> v -> v { } #

Fused multiply-add: @a * b + c@ in a single operation.

vFMS :: (SIMDVec v, Num (Elem v)) => v -> v -> v -> v { } #

Fused multiply-subtract: @a * b - c@ in a single operation.

vFNMA :: (SIMDVec v, Num (Elem v)) => v -> v -> v -> v { } #

Fused negate-multiply-add: @-(a * b) + c@ in a single operation.

vFNMS :: (SIMDVec v, Num (Elem v)) => v -> v -> v -> v { } #

Fused negate-multiply-subtract: @-(a * b) - c@ in a single operation.

vEq :: (SIMDVec v, Eq (Elem v)) => v -> v -> Mask n { } #

Element-wise equality.

vNe :: (SIMDVec v, Eq (Elem v)) => v -> v -> Mask n { } #

Element-wise inequality.

vLt :: (SIMDVec v, Ord (Elem v)) => v -> v -> Mask n { } #

Element-wise less than.

vLe :: (SIMDVec v, Ord (Elem v)) => v -> v -> Mask n { } #

Element-wise less than or equal.

vGt :: (SIMDVec v, Ord (Elem v)) => v -> v -> Mask n { } #

Element-wise greater than.

vGe :: (SIMDVec v, Ord (Elem v)) => v -> v -> Mask n { } #

Element-wise greater than or equal.

vSum :: (SIMDVec v) => v -> Elem v { } #

Sum all elements of the vector (horizontal sum).

vProduct :: (SIMDVec v) => v -> Elem v { } #

Product of all elements (horizontal product).

vHMin :: (SIMDVec v, Ord (Elem v)) => v -> Elem v { } #

Minimum element of the vector.

vHMax :: (SIMDVec v, Ord (Elem v)) => v -> Elem v { } #

Maximum element of the vector.

vShuffle :: (SIMDVec v) => v -> v -> [Int] -> v { } #

Shuffle elements using index mask.

i :: { } #

vBlend :: (SIMDVec v) => (Mask n) -> v -> v -> v { } #

vPermute :: (SIMDVec v) => v -> [Int] -> v { } #

Permute elements within vector.

vRotate :: (SIMDVec v) => v -> Int -> v { } #

Rotate elements left.

vLoad :: (SIMDVec v, Storable (Elem v)) => (Ptr (Elem v)) -> IO v { } #

vLoadAligned :: (SIMDVec v, Storable (Elem v)) => (Ptr (Elem v)) -> IO v { } #

Load from aligned memory (faster).

vStore :: (SIMDVec v, Storable (Elem v)) => (Ptr (Elem v)) -> v -> IO () { } #

Store to unaligned memory.

vStoreAligned :: (SIMDVec v, Storable (Elem v)) => (Ptr (Elem v)) -> v -> IO () { } #

Store to aligned memory (faster).

vGather :: (SIMDVec v, Storable (Elem v)) => (Ptr (Elem v)) -> Vec4I32 -> IO v { } #

Gather: load from indexed locations.

vScatter :: (SIMDVec v, Storable (Elem v)) => (Ptr (Elem v)) -> Vec4I32 -> v -> IO () { } #

Scatter: store to indexed locations.

vMaskedLoad :: (SIMDVec v, Storable (Elem v)) => (Mask n) -> (Ptr (Elem v)) -> v -> IO v { } #

vMaskedStore :: (SIMDVec v, Storable (Elem v)) => (Mask n) -> (Ptr (Elem v)) -> v -> IO () { } #

Masked store.

vAnd :: Vec4I32 -> Vec4I32 -> Vec4I32 { } #

Bitwise AND (for integer vectors).

vOr :: Vec4I32 -> Vec4I32 -> Vec4I32 { } #

Bitwise OR (for integer vectors).

vXor :: Vec4I32 -> Vec4I32 -> Vec4I32 { } #

Bitwise XOR (for integer vectors).

vNot :: Vec4I32 -> Vec4I32 { } #

Bitwise NOT (for integer vectors).

vShiftL :: Vec4I32 -> Int -> Vec4I32 { } #

Shift left (for integer vectors).

vShiftR :: Vec4I32 -> Int -> Vec4I32 { } #

Shift right (for integer vectors).

instance SIMDVec Vec2F32 { }

instance SIMDVec Vec4F32 { }

instance SIMDVec Vec8F32 { }

instance SIMDVec Vec2F64 { }

instance SIMDVec Vec4F64 { }

instance SIMDVec Vec4I32 { }